This invention relates generally to integrated circuit packages and, more particularly, to the fabrication of integrated circuit packages having multiple layers, and the resulting structure. More particularly still, the present invention relates to a fully populated ball grid array integrated circuit package providing a cavity for mounting of a semiconductor die therein and a ground plane element extending about or optionally over the die.
In recent years, semiconductor miniaturization has resulted in the development of very large scale integrated circuit (xe2x80x9cVLSIxe2x80x9d) devices including perhaps thousands of active components thereon. Such devices may typically be encapsulated in a protective package providing a large number of pin-outs for mounting or interconnection to external circuitry through a carrier substrate such as a printed circuit board or other higher-level packaging. The pin-outs for such packages may include, for example, a pin grid array (xe2x80x9cPGAxe2x80x9d), or a ball grid array (xe2x80x9cBGAxe2x80x9d). Both PGA and BGA packages allow for surface mounting upon a printed circuit board. PGA arrays include a two-dimensional array of metal pins that can be directly connected, as by soldering, to the printed circuit board or inserted in a mating socket arrangement carried by the board. On the other hand, a BGA array includes a two-dimensional array of conductive elements formed as, for example, balls, bumps or pillars instead of metal pins. The conductive elements may, by way of example only, be formed as solder (typically lead/tin, although other alloys are employed) balls, may each comprise a relatively higher melting point ball or bump having a solder or other relatively lower melting point outer covering, or may comprise conductive bumps or pillars formed of a conductive or conductor-filled adhesive such as an epoxy.
The bond pads of the semiconductor die disposed within a package must be connected to the printed circuit board via conductors carried by the package, either by direct contact therewith in a flip-chip orientation through conductive balls, bumps or pillars or, alternatively, by intermediate connector elements comprising wire bonds, or TAB (flexible circuit) connections. Finally, the semiconductor die is usually protected on the package by an encapsulant of a plastic, epoxy or silicone material or by being housed in a rigid-walled chamber. Exemplary BGA structures are disclosed in the following U.S. Pat. Nos. 5,397,921, 5,409,865, 5,455,456, 5,490,324, 5,563,446, 5,586,010, 5,594,275, 5,596,227, 5,598,033, 5,598,036, 5,598,321 and 5,708,567. BGA packages are offered by various manufacturers and include, among others, the Tessera xcexcBGA, the Advanced Semiconductor Assembly Technology BGA, the Motorola PBGA (OMPAC), the Yamichi YFlex-LCP, the ProLinx VBGA(trademark), and the IBM TBGA.
The use of BGA packages is becoming widely accepted within the industry due to the ability of BGA designs to accommodate a large number of I/Os, the number of which appears to be ever-increasing for all die types, in the relatively compact area defined within the conductive element array. However, a number of conventional BGA packages are not capable of supporting a fully populated array of conductive ball elements, as the manner in which the die is mounted in the package, or electrically connected to the package traces, requires a conductive element-devoid area in the middle of the conductive element array and so limits the number of solder balls or other conductive elements in the array.
In addition, there is a continued trend in the computer industry toward ever-higher speed integrated circuit (IC) assemblies based upon semiconductor die technology. Such high signal speeds, however, lack utility unless accompanied by suppression of system noise to an acceptable level. The trend toward lower operational signal voltages in combination with such high speeds exacerbates noise problems.
At state-of-the art operational speeds, signal propagation delays, switching noise, and crosstalk between signal conductors resulting from mutual inductance and self inductance phenomena of the conductive paths all become significant to signal degradation. Mutual inductance results from an interaction between magnetic fields created by signal currents flowing to and from a packaged IC die through leads or traces, while self inductance results from the interaction of the foregoing fields with magnetic fields created by oppositely directed currents flowing to and from ground.
Therefore, the integrated circuits carried on a semiconductor die would ideally be electrically connected to conductive traces on carrier substrates such as printed circuit boards and thus to other integrated circuits carried on the same or other such substrates by infinitesimally short conductors, eliminating impedance problems such as undesirable inductance and other conductor-induced system noise.
As a practical matter, however, as the capacity and speed of many integrated circuit devices such as dynamic random access memories (DRAMs) have increased, the number of inputs and outputs (I/Os) to each die has increased, requiring more numerous and complex external connections thereto and, in some instances, requiring undesirably long traces to place the bond pads serving as I/Os for the typical die in communication with the traces of the carrier substrate.
While lead inductance in IC packages has not traditionally been troublesome because slow signal frequencies of past devices render such inductance relatively insignificant, faster and ever-increasing signal frequencies of state-of-the-art electronic systems have substantially increased the practical significance of package lead or trace inductance. For example, at such faster signal frequencies, performance of IC dice using extended leads or traces for external electrical connection is slower than desirable because the inductance associated with the elongated conductive paths required slows changes in signal currents through the leads or traces, prolonging signal propagation therethrough. Further, digital signals propagating along the leads or traces are dispersing or xe2x80x9cspreading outxe2x80x9d because the so-called xe2x80x9cFourierxe2x80x9d components of various frequencies making up the digital signals propagate through the inductance associated with the leads or traces at different speeds, causing the signal components and thus the signals themselves to disperse. While mild dispersion merely widens the digital signals without detrimental effect, severe dispersion can make the digital signals unrecognizable upon receipt. In addition, so-called xe2x80x9creflectionxe2x80x9d signals propagating along the leads or traces as a result of impedance mismatches between the lead fingers and associated IC die or between the leads or traces and external circuitry, caused in part by lead-associated inductance, can distort normal signals propagating concurrently with the reflection signals. Further, magnetic fields created by signal currents propagating through the lead or trace-associated inductance can induce currents in adjacent leads or traces, causing so-called xe2x80x9ccrosstalkxe2x80x9d noise on the latter. While these various effects might be troublesome in any electronic system, the aforementioned trend toward lower voltage systems (currently 3.3 volts) and away from the traditional 5.0 volt systems increases their visibility and significance.
The ever-more-popular BGA die and package configurations described previously serve to exacerbate the noise problems by favoring a large plurality of laterally adjacent traces of substantial and varying lengths extending from adjacent, generally centralized die locations to the horizontally spaced, offset locations of vias extending to solder balls or other conductive elements for securing and electrically connecting the package to a carrier substrate. While a mechanically and electrically desirable packaging concept to accommodate the ever-increasing numbers of I/Os for state-of-the-art dice, long, varying-length, closely mutually adjacent trace runs over the package substrate become abusive in terms of unacceptably increasing real impedance as well as lead inductance (both self and mutual) in the circuit. These trace runs also increase 1) signal reflection in the circuit due to transmission line effects and degrade signal integrity due to the aforementioned, 2) propagation delays, 3) switching noise, 4) crosstalk and 5) dispersion. Further, elimination of a die-attach pad, as in many BGA packages, also eliminates the potential for employing a ground plane under the die, and such a ground plane in any case would not alleviate the problems attendant to use of the long package trace runs.
Therefore, it would also be desirable for a BGA package to accommodate and substantially overcome inductance-related deficiencies so that full advantage of the beneficial aspects of the packaging concept might be realized in a relatively simple, cost-effective BGA package.
The present invention provides a BGA package supporting a fully populated array of solder balls or other conductive elements and exhibiting superior inductance characteristics.
The BGA package of the present invention comprises a base laminate or sandwich of a dielectric interposed between two conductive sheets and which, in turn, are respectively partially covered by two outer insulative layers. One conductive sheet is patterned to provide sites for the conductive elements of an array for connecting the semiconductor die of the package to external circuitry. The other conductive sheet is patterned to define a plurality of conductive traces, each trace extending from an interior die-attach location on the laminate to a location above a conductive site, or to a location suitable for connection to a ground plane for the package. A conductive die-attach pad may be provided at the same time as the traces and communicate with a trace for providing a ground or reference voltage for the semiconductor die. Vias formed with conductive material extend from the traces on one side of the laminate through the dielectric to the conductive element sites on the opposing side. An anisotropically or xe2x80x9cZ-axisxe2x80x9d conductive adhesive layer in the form of a film configured as a frame is then applied over the trace side of the laminate to define an interior region cavity including the die-attach location as well as openings in the frame to allow electrical connection between a conductive stiffener for the package formed as a lid extending over the die-attach location and appropriate conductive traces. The cavity is large enough to leave inner trace ends exposed for connection of bond pads of the semiconductor die thereto by wire bonds, although the invention is not limited to this interconnection technology. For example, the inner trace ends may be patterned as a conductive pad array to connect to intermediate conductive elements such as solder balls or epoxy pillars protruding from the active surface of a flip-chip configured die placed face down on the laminate.
A ground or other voltage reference plane element (hereinafter sometimes referenced generally as a xe2x80x9creference plane elementxe2x80x9d) is secured to the adhesive layer. Various embodiments of the structure of the BGA package of the invention include differing reference plane element structures, which in turn also permit different die enclosure techniques. In each embodiment, however, the insulative layer over the traces is provided with at least one through hole for connection of one or more circuit traces to the reference plane element by mutual contact with the anisotropically conductive adhesive layer.
In one embodiment, the reference plane element is also formed as a frame of like size and shape to the adhesive frame, and placed thereover in alignment therewith, providing a deepened cavity. It should be noted that the use of a relatively thick, and thus rigid, reference plane element permits the use of a flexible, tape-type base laminate in the package, and also provides additional mass to facilitate heat transfer from the semiconductor die. After the semiconductor die is back-bonded to the die-attach location on the base laminate, connections are formed between the traces and the bond pads of the die, after which the die, inner trace ends and connections may be encapsulated with a so-called xe2x80x9cglob topxe2x80x9d of dielectric material, providing physical and environment protection for the encapsulated elements. The reference plane element and underlying adhesive provide a four-sided dam to prevent unwanted lateral encapsulant spread.
In another embodiment, the reference plane element comprises an imperforate conductive sheet extending over the cavity defined by the adhesive frame. If the adhesive is particularly thick, the semiconductor die relatively thin, or a recess is provided in an unusually thick dielectric portion of the base laminate, the reference plane element may be planar in nature, providing a flat lid for the cavity containing the die. If, however, the die thickness plus the height of connecting elements such as wire bonds exceeds the thickness of the adhesive frame, the reference plane element may be formed with a central dome or protrusion over the cavity area to provide adequate clearance. Such a feature may also enhance package rigidity, while permitting use of thinner conductive sheet material for the reference plane element. In this embodiment, the die is connected to the conductive traces of the base laminate before the reference plane element is applied. A thick encapsulant may again be used to protect the die and connections, but it may be preferred, in this instance, to employ a low viscosity dielectric material to merely coat the exterior of the die and the connections to prevent shorting of the latter against the inner side of the reference plane element.
As alluded to previously, yet another embodiment of the invention includes a package configured for use with a flip-chip configured semiconductor die, wherein the upper conductive sheet of the base laminate is patterned with traces having ends configured and arranged in an array of pads or terminals for contact with intermediate conductive elements, such as solder balls or conductive epoxy pillars, protruding transversely from the active surface of the die. An encapsulant may be employed to surround and in-fill between the active surface of the die and the pads, or a reference plane element employed as a lid over the cavity area to enclose the die.